RISC
Of course, there is much more to HPC than RISC.
当然了，关于HPC的知识不只是RISC这方面的。
CISC and RISC architecture aue two dinds of architecture.
微处理器的技术发展过程中，产生了两种不同的体系结构：CISC结构和RISC结构。
CISC and RISC are the two main instruction systems for MCU design.
CISC与R ISC是目前微控制器(MCU)设计的两种主要指令体系。
Godson and other RISC CPU have been made in our country.
面对如此快速发展的硬件,嵌入式软件开发陷入了开发周期过长的困境。
ARM CPU is a kind of advanced 32-bit embedded RISC microprocessor.
摘要ARM处理器是目前公认的业界领先的32位嵌入式RISC微处理器。
RISC is the acronym for "reduced instruction set computing".
英文是“减少指令组的电脑处理”的字首字。
RISC: RISC is the acronym for "reduced instruction set computing".
精简处理:英文是“减少指令组的电脑处理”的字首字。
A reusable and low power RISC CPU IP core design is proposed in this paper.
研究设计了一个可重利用、低功耗的精简指令计算机 (RISC)中央处理器的知识产权 (IntellectualProper ty)核。
Seymour Cray has achieved recognition as a pioneer of RISC architectures.
RISC的设计可以追溯到第一台电子计算机。
While not all RISC machines are the same, they do have many similar qualities.
虽然所有的RISC型机器有很多相似的地方，但是他们并不全部相同。
What is pipelining, anyway? It helps RISC processors run more quickly, but how?
总之，什么是流水线技术呢？它使RISC型处理器运行的更快，那么是怎么实现的呢？
The emphasis in CPU design shifted to raw performance, and RISC became the new philosophy.
cpu设计的重点转到了提高性能上，risc成了新的（设计）思想。
In keeping with their glorious tradition,they will certainly risc against the aggressors.
他们一定会按照他们的光荣传统，起来反击侵略者。
The SMP multi-processors system building by RISC microprocessors is one of the methods of high-performance computer.
RISC微处理器构造的对称多处理SMP多机系统是高性能计算机的一个发展方向。
The emphasis in CPU design shifted to raw performance,and RISC became the new philosophy.
CPU设计的重点转到了提高性能上，RISC成了新的（设计）思想。
RISC chips use a rather small number of relatively simple,fixed-length instructions,always 32 bits long.
RISC芯片采用数量较少、较为简单的固定长度指令，总是32位长。
This paper introduces 32 bit embedded RISC microcomputer that is developed by dint of our country.
本文介绍我国自行研制的32垃嵌入式risc微计算机。
His work on RISC and optimizing compilers won him many awards, not the least of which was the 1987 Turing Award.
他在RISC和编译器优化方面的工作为他赢得了很多荣誉,其中包括1987年的图灵奖。
Now, Linux for POWER brings this convenience to yet another platform, one providing a 64-bit RISC architecture.
现在,用于POWER的Linux也为另一个具有64位RISC体系结构的平台带来了便利。
In keeping with their glorious tradition, they will certainly risc against the aggressors.
他们一定会按照他们的光荣传统，起来反击侵略者。
RISC chips use a rather small number of relatively simple, fixed-length instructions, always 32 bits long.
risc芯片采用数量较少、较为简单的固定长度指令，总是32位长。
Design and implementation of 8-bit MCU I P Core based in system structure of RISC are presented.
介绍了一种基于RISC体系结构的微控制器IP核---8位MCU Core的设计与实现。
In this thesis, an 8-bit MCU based on RISC architecture is designed by Top-Down IC design method.
本文设计并实现了一款RISC结构8位微控制器(MCU)。
The Nios embedded processor is a softcore 16/32 bits RISC CPU optimized for Altera programmable logic devices.
SoPC(Svsetm on Programmable Chip)是基于可编程逻辑的片上系统,Nios处理器是一个基于FPGA的16/32位的软核RISC处理器。
Most RISC processors have faster floating point multiply operations than integer ones.
我见到这样一句话，你的risc处理器是啥?确定没有浮点处理吗?
A RISC microprocessor is developed by using modular design method and VHDL language based on FPGA and EDA technology.
基于FPGA和电子设计自动化技术. 采用模块化设计的方法和VHDL语言,设计一个基于FPGA的RISC微处理器。
For purpose of illustration, a RISC processor that embeds a direct-mapped data cache is employed for the experiments.
为了验证我们的测试方法，我们使用一个拥有直接映射记忆体的处理器来当我们的测试样本。
Von neumann's advice shows that the foundations of the RISC philosophy are not new.
冯.诺依曼的建议表明RISC的基本原理并不是新出现的。
It follows the microprocessor through its iterations to RISC, parallel processing and to today's super-RISC designs.
接下来反复介绍RISC，然后是并行处理技术直到今天的超级RISC设计产品。
MIPS and RISP simulation, together with tools for RISC system development will also be introduced in the course.
介绍用于MIPS仿真及RISP仿真及RISC系统开发的工具。
In this way,the CRAY-1 supercomputer is one of the precursors of modern RISC architectures. 3.
这样看来，CRAY-1巨型机是现在RISC结构的先驱之一。3.
Finally.what is the major difference between a RISC microprocessor and a CISC one?
RISC与CISC最后要讨论的是，RISC微处理器和CISC微处理器之间的只要区别何在？
In RISC OS SWIs are used to access Operating System routines or modules produced by a 3rd party.
在 RISC OS 中使用 SWI 来访问操作系统例程或第三方生产的模块。
A poor VLIW compiler will have a much greater negative impact on performance than would a poor RISC or CISC compiler.
一个差的VLIW编译器对（系统）性能的负面影响超过差的RISC或CISC编译器的影响。
To prevent 1 death, the number needed to scan was 17 based on TRISS and 32 based on RISC calculation.
为了预防1件死亡，根据TRISS，需要扫描17人，根据RISC，需要扫描32人。
Hewlett-Packard's Precision Architecture (PA-RISC) was another early commercial RISC.
惠普的精密架构(PA-RISC)是另一个早期的商业化RISC系统。
In this way,the CRAY-1 supercomputer is one of the precursors of modern RISC architectures.
这样看来，CRAY-1巨型机是现在RISC结构的先驱之一。
It is still a standard part of the POTUS motorcade and I don't believe considered part of the RISC team.
它仍然是一个标准的一部分，博图士的车队和我不相信认为是RISC的团队。
The latest RISC processor also guarantees high throughput speed which is perfect for large graphic data.
最新的RISC处理器进一步保证了快速的打印，并能够完美打印出较大的图片信息。
The following characteristics are typical of pure RISC architecture and most designers agreen on them.
下面是纯粹RISC结构的典型特性并得到大多数设计师的赞同。
Rather,RISC tries mainly to reduce the average number of clock cycles per instruction(CPI).
两种结构均想通过使用高速技术来提高时钟频率。
Samsung S3C2440A SOC RISC Microprocessor test program that demonstrates how to code most peripherals on the chip.
(译)：三星S3C2440A RISC微处理器的SOC测试程序，演示了如何代码最外围芯片上。
MPC555 is a 32-bit microcontroller, with RISC CPU in it and PowerPC compatible instruction set architecture.
MPC555是一款PowerPC体系结构、采用RISC CPU技术的32位微控制器。
Network processors overcome the limitations of these two approaches by combining the programmability of RISC processors with the performance of ASICs.
网络处理器通过把RISC处理器的可编程性与ASIC的性能结合起来，克服这两种方法的局限性。
The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
OR1200是一种32位、标量、哈佛微体系结构、5级整数流水线RISC，支持虚拟存储器和基本的DSP功能。
VLIW chips can cost less,burn less power and achieve significantly higher performance than comparable RISC and CISC chips.
与RISC和CISC芯片相比，VLIW芯片的成本低、功耗低、并能获得更高的性能。
RISC processors,because they are software-programmable,provide the flexibility to get adapted to the rapidly evolving data communications market.
RISC处理器由于是可编程的，故提供了灵活性，以适应快速发展的数据通信市常
Gives techniques for improving the speed of matrix multiplication by more than a factor of two on superscalar RISC processors.
讲述在超标量RISC处理器上用大于二的因子来提高矩阵相乘的速度的方法。
POWER stands for Power Optimization With Enhanced RISC and is the main processor in many IBM servers, workstations, and supercomputers.
POWER是Power Optimization With Enhanced RISC的缩写,是IBM的很多服务器、工作站和超级计算机的主要处理器。
The RISC architecture soon came to dominate the workstation and embedded markets, and John Cocke moved on to other projects.
RISC体系结构在工作站和嵌入式市场中很快占据了主导地位,John Cocke之后又转入其他项目的研究之中。